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Reliability-aware simulation and validation for analog/mixed-signal circuits in sub-32nm CMOS

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is an integral part of the electronics technology of today and is used on a daily basis by billions of users worldwide through personal computers, phones and cars, among others. Due to its massive usage, the reliability of the MOSFET is a critical part of its development and research. This study focuses on the
effects of random variability on the MOSFET and the evolution over time. The Bias Temperature Instability (BTI) degradation mechanism and the Random Telegraph Noise (RTN) effect are the two main subjects covered in this thesis. Both are caused by electrical traps found in the MOSFET, and can generate mismatch from device to device that changes over time. The effects of BTI and RTN on the transistor are collectively called time-dependent mismatch or variability, to distinguish them from the time-zero mismatch effects caused by the fabrication process.

Two chips have been designed, fabricated and measured to investigate the effects of the time-dependent mismatch on transistors in an advanced 28nm CMOS technology. The first chip is a transistor array containing 54,432 nMOS and pMOS individually-selectable transistors of six different geometries. With this chip, we show that transistor arrays are very effective to characterize both timedependent and time-zero mismatch up to a high precision, or more specifically 3-sigma in our case. While this design provides access to each individual transistor within the array enabling several different measurements, the characterization of the RTN time constants remains a tedious and time-consuming task.

The second test chip uses on-chip amplifiers, filters and digital blocks designed around the transistor array, to facilitate the extraction and the analysis of these time constants. Even thought the RTN amplitude is lost by the amplification into a digital signal, the temporal data are preserved. This trade-off has been made to enable real-time on-chip measurement and analysis of the RTN time constants.

Since a large part of this thesis focuses on the measurement of stochastic BTI and RTN effects using transistor arrays, three different measurement methods have been compared. The first method is the 2-point Measure-Stress-Measure (2-point MSM), the second is the Time-Dependent Defect Spectroscopy (TDDS) method, and the third is the fine-step Id-Vg method. When applied to transistor arrays, we show that the 2-point MSM method is the fastest while the TDDS method is the most accurate.

Finally, all the data collected through measurements have been used to study the area scaling effect of BTI and RTN, which is important for analog designs. By studying the compound Poisson-exponential distribution, which is used to model the measured data, methods are provided to estimate the impact of time-dependent mismatch on analog designs in simulations. This has been
demonstrated through the simulation of two cases: a ring oscillator and a flash analog-to-digital converter.

As discussed in the thesis, the impact of the time-dependent mismatch on analog integrated-circuit designs can be significant. It is therefore important to accurately characterize, model and predict the time-dependent mismatch in analog designs that use advanced CMOS technology nodes. 

Date:3 Sep 2013 →  29 Aug 2018
Keywords:Random Telegraph Noise, RTN, Bias Temperature Instability, BTI, Transistor mismatch, Time-dependent mismatch, Analog IC, Simulation, CMOS
Disciplines:Nanotechnology, Design theories and methods
Project type:PhD project