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Radiation tolerant, All-Digital Frequency Synthesizers

High performance clock generation or frequency synthesizers are used in almost all of today's state-of-the art systems. Environments containing ionizing radiation such as high-energy physics experiments (like the ATLAS and CMS detectors at the LHC at CERN), nuclear fusion reactors and space tend to increase the performance of their systems towards current state-of-the art achieved circuits. However, ionizing radiation degrade the silicon performance over time and generates so called single-event effects in the devices which disturb the signals in the circuits. Historically, multi- GHz clock generators and frequency synthesizers were designed in a traditional analog way but developments in all-digital Phase Locked Loops (PLLs) have shown competing performances in terms of noise, power consumption and flexibility. Furthermore, these circuits may be more suitable in the targeted applications where ionizing radiation is a concern. In this project, you will be doing research on low noise, radiation hardened all-digital PLLs. During this work, circuit developments will be done, and new architectures will be investigated to mitigate single-event effects in all-digital PLLs. The PhD focus both on the analog, radiation aware design of digital controlled oscillators (DCOs) and digital architectures for the loop control. These mixed signal circuits will be designed, processed and experimentally tested with ionizing radiation to verify the innovative work done in this PhD. The circuit techniques target better than 500 fs jitter with less than 10 mW power consumption. Radiation levels beyond 5 MGy are expected with an SEU tolerance above 100 MeVcm2/mg.

Date:31 Aug 2018  →  Today
Keywords:PLL, Radiation-tolerant integrated circuits
Disciplines:Applied mathematics in specific fields, Modelling, Multimedia processing
Project type:PhD project