Optimization of ferroelectric memory cells for next generation SCM
Because of the ever increasing demand for higher density memory in current electronic systems, nonvolatile memories have gone 3D by stacking many cells vertically on one single chip. However, this (Flash) roadmap suggests a doubling of the number of layers every 2-3 years to keep up with Moore’s law. Moreover, due to the low performance of these memories there is room for new memory technologies that can better bridge the gap between DRAM and Flash in order to optimize the system performance. Therefore, alternative (nonvolatile) memory solutions will be needed in the future. One possible solution to this problem is the ferroelectric field effect transistor (FeFET) which allows for fast and low voltage low power nonvolatile storage. Another one is the ferroelectric capacitor which, combined with a regular access transistor, can provide a nonvolatile memory closer to DRAM. However, many challenges are remaining to be solved before entering the market in a real product, such as controlling the domain configuration and the associated variability, wake-up and imprint effects in the ferroelectric material and various device performance issues such as nucleation delay, cycling and retention. The purpose of this project is to study and explain the characteristics of 3D FETs as well as capacitors from the point of view of SCM (Storage Class Memory) specifications as set forward by the systems community. Secondly, new device architectures can be proposed based on this basic understanding of the cell’s operation and implemented in state-of-the-art CMOS technology for the Gigabit and Terabit era.