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Novel radiation hardened All-Digital Phase-Locked Loop/Clock-Data Recovery (ADPLL) architecture design for 65nm CMOS

The main goal of this project is the development of an All-digital PLL/Clock-Data Recovery(ADPLL) core with a wide-range programmable output frequency to support different space applications. The ultimate goal of this project is the research on a customizable PLL/CDR IP block that addresses the needs of various applications to reduce the design effort by centralizing the PLL/CRD expertise in one project. The objective is to present an IP core that is open and highly adjustable to meet the needs of different systems.

Date:1 Dec 2018  →  Today
Keywords:All-digital PLL/Clock-Data Recovery(ADPLL) core
Disciplines:Signal processing