New memory topologies enabled by IGZO in the BEOL for DRAM application

For the last few decades, the scaling-down of technology has been keeping the pace with market demands in the semiconductor industry. However, we have a lot of problems related with the continuing the scaling-down. More specifically, DRAM domain is facing lots of issues in front of device scaling.  As well known, DRAM cell is composed of 1-cell transistor and 1-capacitor. Based on this configuration, the critical challenges are coming from two aspects. Firstly, with the technology scaling, it's not easy to maintain the existing performance of cell transistor with higher on-current for performance and lower off-current for the retention time. Secondly, the cell capacitor is also exposed to the big challenge, which strongly dominates the absolute sensing margin. So, the cell capacitance should have enough number combined with bit line loading. In this work, IGZO-FET is proposed to replace the cell transistor and one of big flavours from IGZO-FET is a super-low leakage and BEOL-friendly feature. Based on these benefits, new memory will be explored with different bit cell configurations:1T1C, 2T0C and 2T1C. In conclusion, the target application of IGZO-based new memory is for DRAM replacement which will be validated with Si-measurements. Also, these explorations will cover not only 2D-array but also 3D-array configuration and it can be a breakthrough to continue the scaling-down in DRAM domain.