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Project

Massive Parallel Readout Circuits for In-Vivo Signal Acquisition

Multi-electrode neural recordings are becoming standard practice in basic neuroscience research, and knowledge gained from these studies is beginning to enable clinical and neuroprosthetic applications. However, there is clear need from neuroscientists towards higher number of recording sites per given area, low-power dissipation, and wireless data connectivity to facilitate better and more accurate measurement of neural signals. In parallel, the requirements of signal quality and data rate are continuing to be the key specifications for the integrity of the neural signals. Unfortunately, the signal quality, miniature size, and low-power dissipation are contradicting requirements for the realization of the neural probes, especially in terms of hardware design. As the noise of analog circuits increases with reducing area, new solutions are required for the implementation of miniature size readout arrays. On the other hand, the increasing number of electrodes leads to larger amount of data, which in turn increases both the signal processing power and the data transmission power.

The purpose of this PhD topic is to explore different design methodologies and architecture to achieve miniature and densely packaged neural recording arrays that will meet the signal quality constrains of neuroscientists and power dissipation constrains of the available power resources. This will require innovation in the field of integrated circuit design and the investigation of new techniques to reduce the size and power dissipation of the readout circuits. In order to achieve this target, the candidate is expected to investigate in detail the state-of-the-art, explore new and innovative system and building block architectures, and come up with new concepts and architectures that will enable to increase the number of recording sites for neural monitoring systems. He will also be looking at system design challenges to handle the increasing amount of data and investigate lowpower methodologies for wireless data transmission.
 

Date:1 Feb 2013 →  16 Apr 2018
Keywords:neural probe, CMOS
Disciplines:Nanotechnology, Design theories and methods
Project type:PhD project