Integration of a IIIV p-channel tunnel-field-effect transistor for ultra-low power nano-CMOS applications.

The Tunneling Field-Effect Transistor (TFET) is a promising candidate for future low-power logic applications. The carrier injection mechanism of the TFET is quantum mechanical Band-To-Band Tunneling (BTBT), which is accompanied by an energy filtering mechanism. This filtering allows switching from the off-state to the on-state using a lower supply voltage than the MOSFET, and hence reducing the power consumption of integrated circuits.

To identify favorable III-V TFET configurations and guide TFET fabrication, semi-classical and quantum mechanical simulations are crucial. However, there is uncertainty on the accuracy of the models relevant to TFET and on their input parameters. The topic of this thesis is the experimental calibration of the models for the desired BTBT as well as the ones of relevant parasitic mechanisms, like Shockley-Read-Hall and trap-assisted tunneling due to bulk traps. We also characterize Field-Induced Quantum Confinement (FIQC) and the energy band alignment of heterojunction TFET. We achieve this using tunnel diodes and MOS capacitors, which are easier to fabricate and characterize than complete TFETs. Our work enables improved understanding of experimental TFET data and more accurate performance prediction of III-V heterojunction TFET.