Heterojunction Tunnel FETS using 2D Materials as Channel
2D materials research has been shifting towards novel electronic and optical applications apart from conventional MOSFETs. Their atomically flat surfaces and self-passivated layers offer potentially defect free inter-layer tunneling. Band-to-band tunneling field effect transistors (TFET) have caught the attention of industry and academia for over a decade in CMOS scaling with the promise of obtaining a steep Subthreshold Swing, SS < 60mV/dec at room temperature
Achieving a low supply voltage and obtaining a high enough on current and steep SS are crucial in 2D TFETs for future CMOS technologies. However when compared to simulations, experiments are still far fetchedfrom reaching the required performance. Hence, the goal of this thesis is to systematically identify and characterize the parasitics limiting high ION and steep SS in 2D TFETs. We achieve this by fabricating 2D heterojunction TFETs based on MoS2-MoTe2 and ReS2-BP. The parasitics that we focus on are 1) Schottky barriers at the contacts, 2) impact of different current components on TFET performance 3) impact of multiple layers on BTBT and gate electrostatics, 4) device gate configuration on BTBT transport, 5) impact of indirect and direct BTBT on ION and SS, 6) point tunneling and 7) Material anisotropy on carrier transport.
In the first part on MoS2-MoTe2 TFETs, we perform our experiments using three different gate configurations. These allow us to address the transport mechanisms characteristic of each configuration. Due to our inability to dope the contact regions, we observe significant degradation of BTBT current. In order to isolate the contacts’ influence, we then introduce a contact gated architecture that decouples the influence of the contacts from the channel. We also assess the long tunneling paths arising from tunneling across multiple 2D layers using Quantum transport simulations. These findings provide additional insights on investigating the impact of gate configuration and indirect tunneling on the device performance.
In the second part, BP-ReS2 TFETs are fabricated with different flake thicknesses to identify the most favorable configuration for TFETs. Further optimizations are demonstrated to reduce the equivalent oxide thickness (EOT) of the gate dielectric to obtain a lower SS and to reduce the gate leakage. From the electrical measurements, we demonstrate that tunneling happens only at the edge of the heterojunction, which is also known as point tunneling. Finally, we study the anisotropic transport in BP-ReS2 TFETs by investigating the anisotropy in BP on the BTBT current and the SS of the TFET. Combining all the outcomes of this work, the thesis thus provides the necessary framework to implement 2D TFETs for beyond CMOS technology.