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Project

Ga + B co-doped Si1-xGex: Low Temperature Epitaxial Growth and Physical Characterization in view of Advanced MOS Devices

Current downscaling of MOS devices goes together with modifications of the transistor geometry, the use of new materials and the introduction of new device concepts. In classical charge-based devices, contact resistance is one of the key parameters determining device performance. Scaling means a reduction of transistor dimensions. The reduction in Source/Drain (S/D) contact area leads to an increase in contact resistance. New approaches are required to significantly reduce contact resistance. The right materials, with controlled doping and the best process technology, are key parameters to meet this challenge. This triggered the research community to assess alternative dopants for the Si1-xGex S/D layers such as Ga in case of pMOS devices. Encouraging improvements in contact resistance have been reported for Ga-implanted Si0.4Ge0.6 layers. However, the associated laser anneal requires a too high thermal budget and, on patterned wafers, the doping profile is far from optimal. A preferred processing method is the epitaxial growth of in-situ doped materials. It offers low temperature processing and conformal doping. Moreover, selective growth offers an elegant integration approach by limiting the deposition to open semiconductor areas. In this project, I will generate the fundamental understandings of low-temperature growth of group-IV semiconductors using Chemical Vapor Deposition, with a special focus on Ga + B co-doped SiGe for the implementation in < 5 nm node CMOS.

Date:20 May 2019  →  Today
Keywords:Contact resistance, CVD, CMOS, Epitaxy, Source/Drain
Disciplines:Semiconductors and semimetals
Project type:PhD project