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Project

Electrical and physical characterization of trap states at the SiC/gate dielectric interface in SiC metal-oxide-semiconductor field-effect transistors.

This is a research project financed by the Vlaio agency for innovation and entrepreneurship (VLAIO - Vlaanderen). The project was subsidized after selection by the expert panel. The project is conducting in collaboration with Flemish Industry.
Date:1 Apr 2019 →  31 Mar 2023
Keywords:FIELD-EFFECT TRANSISTORS, ELECTRON PARAMAGNETIC RESONANCE (EPR)
Disciplines:Electronic (transport) properties, Condensed matter physics and nanophysics not elsewhere classified
Project type:Collaboration project