Efficient Methods for Validation and Testing of Analog/Mixed-Signal ICs
Validation and testing are important steps in the design of analog and mixed-signal integrated circuits. Both require extensive and repeated simulations of the circuit in the light of process/supply/temperature variability and in the light of the possible fabrication defects. All this causes these design steps to have prohibitive CPU times in practice, especially for larger circuits. The goal of this PhD project is to investigate and demonstrate more efficient, alternative techniques that replace the time-intensive repeated simulations, by exploring techniques such as from the field of formal verification and interval bounding. This should then result in a more efficient approach with good scalability.