Efficient design of ultra-low power nearthreshold digital processors.

An increasing amount of ’smart’ electronic devices is filling our everyday lives and the environment around us. The convenience of these devices grows with better functionality, processing power and battery life. The main target in developing digital circuits and systems for these applications has shifted towards energy efficiency. Especially when periodical battery replacement is impractical, expensive or impossible, minimum energy considerations come in to play. The focus of this dissertation is to realize minimum energy operation in these digital systems.

The energy consumption of a digital CMOS circuit can be reduced by decreasing the supply voltage. Together with the supply voltage, the speed performance degrades. The result is a trade-off between energy consumption and speed performance, demonstrating an optimum called the minimum energy point. For digital logic circuits, operation at this optimal point comes at ultra-low supply voltages. A more than significant energy reduction can be achieved in this way. Operation at ultra-low supply voltages in CMOS technology poses several challenges. Typically, normal circuit functionality is compromised, let alone speed performance. Moreover, ultra-low voltage operation is highly susceptible to variations in the fabrication process, temperature and supply voltage.

This dissertation aims to realize digital systems in CMOS technology with an ultra-low energy consumption that have a high speed and a high tolerance for variations. The challenges such a system faces are tackled on three levels: the circuits, the design strategy and the architecture.

At the circuit level, the transistor properties and the effects they have on circuits are investigated, demonstrating where circuit improvements can be made. The circuit topology investigated in this work demonstrates a high speed and a high variation tolerance. These improvements are applied in the logic gates and flip-flops that make up digital systems.

Considering design strategy, an efficient design flow that can leverage this circuit topology to its maximum ability is necessary. The logic gates and flip-flops are poured into standard cells, creating timing and power models that enable a standard cell design flow. The conventional VLSI design flow is adapted in order to synthesize register-transfer language with this standard cell library and to do physical implementation. This enables a fast design cycle and provides system level insights in the minimum energy point of the circuit-under-test.

Variation-resilient building blocks only get you so far. Process variations result in highly unpredictable ultra-low voltage systems. While this is usually managed by incorporating margins, an adapted system architecture can overcome these process variations in a generic way. By augmenting the system pipeline with error detection and correction flip-flops, real-time information on the system criticality is gathered by decreasing the supply voltage to the sub-critical level and detecting the timing errors. In the mean time, correct operation is guaranteed through error masking. The error information is processed at the system level and leverages a dynamic voltage scaling loop to continuously operate in a near-failure regime. The result is a predictable ultra-low energy system.

These three levels are put to practice in three increasingly complex prototypes. The system-under-test is a 32-bit microcontroller architecture commonly used in consumer applications. Silicon implementation and measurement results of these prototypes demonstrate the validity of the techniques discussed in this dissertation. This top-down/bottom-up approach that incorporates ultra-low voltage variation-resilient considerations on all levels results in state-of-the- art performance. As such, this dissertation is a worth-while step toward the adoption of these ultra-low energy digital systems in the smart devices in our environment.