Device-Circuit Co-Design of 2D Material Based Devices for Future Electronics
Over the past few decades, the miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) has played an instrumental role in advancing the field of electronics. More recently, as the transistor dimensions are reaching to a few atoms, it is becoming increasingly challenging to downsize the conventional Silicon (Si) transistors without sacrificing the performance. Thus, in order to continue with the scaling of these high-performance transistors, alternate materials and device architectures are being explored to replace modern strained-silicon (s-Si) FinFETs. While III-V materials such as InGaAs promise higher electron mobilities and injection velocities than s-Si, emerging two-dimensional (2D) materials and nanowire (NW) device architectures promise better immunity to short-channel-effects. This PhD investigates the prospects of these 2D material based devices for high performance future electronics. It focuses on the selection of right 2D material and optimum device designs for 2D material transistors, and benchmarking of 2D transistors with the state-of-the art s-Si and InGaAs based MOSFETs. It was found that although 2D material n-MOSFET promise more energy-efficiency compared to state-of-the-art s-Si FinFET in sub-0.7 V supply voltage regime, it cannot match the speed of s-Si based Fin and NW FETs for higher supply voltages, unless 2D MOSFETs are stacked in a monolithic 3D fashion.