A design process for parallel data processing in embedded systems.

The application domain of embedded systems is in need of design processes for parallel data processing in FPGAs. This project will develop a concrete design process based on a case study of simple pattern recognition by means of a high-level synthesis tool. This will lead to new generic insights in the design process of FPGA-code, as well as the efficient development of algorithms being used in current particle physics experiments.

Keywords:EMBEDDED SYSTEMS, PARALLEL DATA PROCESSING, FPGA, HIGH LEVEL SYNTHESIS

Disciplines:Applied mathematics in specific fields, Elementary particle and high energy physics, Quantum physics, Communications, Communications technology, Electronics, Nanotechnology, Design theories and methods, Computer hardware, Computer theory, Scientific computing, Other computer engineering, information technology and mathematical engineering

Project type:Collaboration project