Power-efficient Wide-bandwidth Continuous-time ∆Σ CMOS ADCs for Wireless Communications

The explosive development of wireless communications sets stringent requirements on the design of analog-to-digital converters (ADC) in terms of high bandwidth and low power consumption. This PhD dissertation will conduct research on high-speed and energy-efficient ADC in nanometer CMOS technologies. The objective is to explore architectures that fully make use of the advantages of the CMOS technology scaling. Different from prior work in Delta-Sigma ADCs, the key idea of the research is to use a low-power SAR quantizer to replace the power-hungry FLASH quantizer with new mismatch-canceling technique, hence largely improving the power efficiency of the entire converter as measured by the figure of merit (FoM).

The PhD work covers the full custom IC design flow. The research methodology of this dissertation is as follows: 1. Behavioral modeling of the modulator architecture and their nonidealities. 2. System-level optimization of the Delta-Sigma ADC, by adjusting the systematic parameters. 3. Circuit-level design and implementation of the proposed ADC prototype. After tapeout, the chip will be measured to verify the proposal design. The experiences may lead to other designs following the same design methodology.