< Back to previous page

Project

Matchmaker: Marrying Emerging AI Algorithms to Emerging AI Hardware through Compilers

For the efficient and privacy-oriented processing of sensor data in “the edge”, increasingly more artificial intelligence is used (often in the form of neural networks) on ultra low power microcontroller platforms. Energy efficiency is critical for these platforms as they often have to work for extended periods of time on a single battery charge. Efficient code generation for neural networks on these platforms is often difficult. Current methods are often aimed very directly to the hardware. This makes the code less portable to other devices, and often a lot of manual steps are needed in the code generation process. It also often requires the application designers to be very aware of the hardware platform, which makes it difficult for them to program these new types of devices. This thesis investigates tools (compilers ) that make it easier for the application programmer to run their neural networks efficiently on these new ultra-low-power platforms. We investigate which program structures make it possible to do this in an efficient, portable and preferably automatic way. We also investigate whether the support of these tools might require changes on the hardware or the application side, to further improve optimal deployment from the software on the hardware.

Date:1 Oct 2021 →  Today
Keywords:Ultra-low-power embedded systems, Artificial Intelligence, Compilers, Internet Of Things, Hardware Software Co-design
Disciplines:Embedded systems, Pattern recognition and neural networks, Processor architectures, Computer architecture and organisation
Project type:PhD project