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Patent

Method for encapsulating a device in a microcavtiy

Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10nm -500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.
Patent Publication Number: EP1843971
Year filing: 2006
Year approval: 2016
Year publication: 2016
Status: Assigned
Technology domains: Micro-structure and nano-technology
Validated for IOF-key: Yes
Attributed to: Associatie KULeuven