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Drain extension region for tunnel FET

A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.
Patent Publication Number: US9704992
Source: USPTO
Year filing: 2016
Year approval: 2017
Year publication: 2017
Status: Assigned
Technology domains: Semiconductors
Validated for IOF-key: Yes
Attributed to: Associatie KULeuven