Advanced Electrical Characterization with Machine Learning: Extracting Device Information with Less Data

MetalOxide Semiconductor Field-Effect Transistors (MOSFETs) are an essential building block for all electronic systems today. The integration of a large number of tiny MOSFETs into a compact chip resulted in smaller, quicker, and less expensive circuits than discrete electronic components-based circuits. These transistors are composed of single gates on Silicon bulk or on insulators (SOI), tri-gates (FinFET), and gate-all-around called GAAFET, nanosheets, or nanoribbons. New materials like ultra-thin WS2 introduced into disruptive architectures are today in the research pipeline to enter into production by 2030-2040. To provide a few figures on the importance of the market of advanced MOSFETs, while in 2020, the Global Gate All Around FET technology Market share was $22.14 million, it is predicted to reach $472.25 million by 2030, with North America being the most significant market share in the Global GAAFET technology market and Asia being the main fabrication center of these advanced transistors. Integrated Circuits testing has contributed to a significant portion of nanoscale technologies' total manufacturing and cost. The reason behind among others is that silicon characterization and parameter extraction flow utilize a large area overhead due to the complexity of different test structures to cope with a surge of defects resulting from unprecedented complex fabrication flows for GAA devices for instance. To greatly reduce the time and cost required for measurement of the on-chip test, an early detection of the numerous sources of variability in advanced process technologies is a key challenge to ensure robust circuit performance as well as high manufacturing yield. Ultimately, there is an absolute need to reverse the current trend that it is impossible to proceed with current-voltage measurements for every on-chip monitoring device on a significant amount of dies in a wafer. In this work, we aim to search for the electrically active and non-electrically active defects created during the complicated fabrication steps of the advanced devices leveraging machine learning algorithms, and state-of-the-art physical characterization techniques combined with our expertise in physic-aware device modeling. Also, we would like to offer a new machine learning architecture that reproduces as accurately as possible Id-Vg outputs of the advanced transistors processed in our prototype R&D line. This will use their physical features and replicates the dimensions, materials, structures, underlying physics, and electrical characteristics. In this PhD, we plan first to further develop an existing software that provides an efficient classification (functional or not functional device) of the MOS field-effect transistors depending on the shape of their 4-terminal I-V output characteristics. To improve greatly its prediction accuracy, a literature search of state-of-the-art deep learning methods such as Yolov5, ResNet, EfficientNet, and DeciNet will be performed and additional modules will be plugged into the CNN-based AI software and tested. Data of functional devices from production line filtered by ML classifier will be collected. We will apply the most recently-developed data mining techniques to find not only a correlation between data but also common patterns. In the second part of the thesis, electrical characteristics of functional devices will be combined with the physical constraints to create a ML model for producing potential electrical characteristics data of the prototype devices. The goal will be to offer an early detection of the hard failure of the devices but also classified defects and/or defects patterns that may impact or not the output characteristics of the final advanced pre-production transistors. Finally, the learning on the electrically active defects associated with the new device integration schemes, new materials, or new process recipes will be ported to the design technology co-optimization (DTCO) level to help the designers to propose variability controlled SRAM circuit design for instance.