Hardware efficient microarchitecture and quantum error correction codes for large scale quantum processors

With the recent demonstration of quantum supremacy, quantum computing is entering the era of Noisy Intermediate Scale Quantum computing (NISQ), where dozens to several hundreds of artificial quantum objects interact in such a way as to perform computationally intractable yet trivial tasks such as simulating their own behavior [1]. Yet, even the most optimistic estimates assume that many millions of qubits will be required for properly executing meaningful tasks such as quantum chemistry. At the heart of this discrepancy is the enormous overhead required to mitigate the effect of errors and to realize fault-tolerant quantum computation [2]. At imec, we are therefore developing methods and technology to improve the prospect of scaling up quantum processors to truly useful levels, by leveraging the advanced process control and extreme accuracy present in advanced microfabrication methods such as those present in semiconductor foundries. By homogenizing the qubits (reduced variability) and removing physical sources of noise and decoherence (surface, interface, defect control), we aim to increase the fidelity of the qubits and facilitate more robust control. Our efforts thus far have focused on superconducting [3] and spin qubits [4], both of which were shown to benefit from the advanced fabrication methods available. The aim of this thesis is to help design microarchitectures and optimized error correction schemes, tailored to the hardware platforms under development. By exploiting asymmetries in the noise behavior of particular qubit designs, recent studies showed that error correction overheads could be significantly reduced [5] compared to more generic codes that assume ‘worst case’ behavior. Potential variants will be investigated that are compatible with the hardware under development, and that try to exploit specifics thereof. One particular example involves the possibility of designing error correction schemes tailored to time-division multiplexed control of qubits [6]: in view of the massive I/O problem, many groups worldwide (including imec) are looking at multiplexed qubit control as a potential scaling mitigation mechanism. Can codes and microarchitectures be designed that exploit such multiplexed behavior? [1] F. Arute et al., Quantum supremacy using a programmable superconducting processor, Nature 574, 505 (2019) [2] S. Devitt et al, Quantum error correction for beginners, Rep. Prog. Phys. 76, 076001 (2013) [3] M. Devoret Superconducting circuits for quantum information: an outlook, Science 339, 1169 (2013) [4] L. Vandersypen et al., Quantum computing with semiconducting spins, Physics today 72, 38 (2019) [5] S. Puri et al., Bias preserving gates with stabilized cat qubits, Science Adv. 6, 34 (2020) [6] R. Acharya et al., Scalable 1.4 µW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements, VLSI symposium 2022 (invited)