Fault Tolerant RISC-V CPU in Advanced CMOS Nodes

1. State of the art and problem-setting Modern microprocessors used in radiation harsh environments are becoming more vulnerable to transient faults which can lead to errors in critical data and control paths of digital designs. In addition, because further decreased geometries, integrated circuits are becoming more susceptible to soft errors and radiation inference, hence resulting in reduced reliability. Several redundancy techniques are available to increase the reliability of electronic designs within these harsh environments. System-level redundancy is the most common used technique, and we can distinguish three classes of redundancy techniques, including temporal, information, and spatial redundancy. Temporal redundancy relies on multiple executions of the same task, followed by comparing the results of all executions before defining the output. Information redundancy consist of adding extra bits to the data to detect and correct data in the event of an error. Spatial redundancy consists of multiple instances of the same module, followed by a comparison of their outputs to determine the values present in the system. However, these methodologies come with an extra cost both in area and power consumption. 2. Objectives and research questions Stated in the problem setting, system-level redundancy techniques come with an extra cost in area and power consumption. Because of this, the question can be asked if redundancy can be moved from a system towards a micro-architectural level while maintaining or improving performance and reliability in combination with a reduction of resource utilization and power consumption. The objective is to develop a custom RISC-V fault-tolerant architecture that includes different techniques to mitigate faults. Furthermore, the architecture should be compliant with the RISC-V ISA, debug, and trace specification and can be produced in a state-of-the art bulk Complementary Metal Oxide Semiconductor (CMOS) process nodes.