Practical Fault Attacks on Cryptographic Devices

There are different approaches to attack a cryptographic device. One can choose to attack the cryptographic algorithm that is used using mathematical techniques, the other is to exploit the physical properties of the device the algorithm is executed on. The latter ones are called physical attacks. One sort of these physical attacks is called fault injection attacks where an attacker tries to inject certain faults in the algorithms execution. The injection of these faults results in the leakage of secret information. There are many ways to inject faults in electronic devices but in this thesis the focus will lie on the use of laser beams and electromagnetic (EM) pulses to inject faults. The advantage of using these techniques is that they are localized and difficult to detect by the device under attack (DUT). Both laser and EM fault injection are becoming more and more affordable and are well within the reach of a motivated attacker. Many techniques are proposed to exploit faults, but most of these techniques are only verified in theory or tested on devices which were specifically tailored for the attack. The goal of this thesis is to preform attacks on devices that are used in the real world. Thus devising attack methods that allow to efficiently test whether or not a device is vulnerable for certain fault attacks and what can be done to mitigate this vulnerability. Current attacks mostly focus on injecting faults directly in the control flow or the data stored on the device. Modern system on chips (SOC's) however have a number of components that are used to control the operating conditions such as voltage and frequency of the chip. The exploitability of these components to mount fault attacks will also be investigated. A second part of the research, besides proving that certain devices are insecure when exposed to fault attacks will be verifying the security of fault resistant designs made by other researchers. This will be done by exposing the design to a strong attacker who has full control over the DUT and knows the implementation details of the fault resistant design.

Publication year:2021

Accessibility:Open