Cryptography secured against physical attacks

Passive and active physical attacks are real-world threats for cryptographic implementations. With the possible access to the device executing a cryptographic algorithm, an attacker can collect information through side-channels or inject faults. A common countermeasure is masking against side-channel attacks, and implementing redundancy or infection against fault attacks. While there exist countermeasures against side-channel attacks (i.e. masking) that are provably secure, the countermeasures against fault attacks are mostly based on heuristics and specific to the attack type. Moreover, the duality relation between the side-channel and fault attack countermeasures (i.e. redundancy increases the attack surface for side-channel attacks, masking increases the attack surface for fault injection) complicate implementing countermeasures protect against both attacks.

Considering the lack of attention given to higher-order fault attacks, and combined attacks (and the increase in the research focusing on injecting multiple faults in one computation), this research will focus on protecting cryptographic implementations against higher-order fault attacks, and combined attacks. Expected conclusions from this research are provably secure countermeasures against higher-order fault attacks and combined attacks with realistic adversarial models.