Advanced Architectures for Time-based Analog-to-digital Converters

Analog-to-digital converters (ADCs) are an important building block for many modern electronic applications. During the last decade there has been a clear trend towards combining more and more components on a single chip, creating so-called systems-on-chip (SoCs). These SoCs are highly complex and contain both analog and digital components, including ADCs. SoCs have become incredibly popular since they are much cheaper and smaller than the discrete systems that were used in the past. Today they are used in every smart phone and many other applications as well.We have come to expect a constant increase in performance of our electronic devices, which is made possible by ever smaller transistors and lower supply voltages, a trend that makes digital circuits both faster and more energy efficient. However, lower voltages are not beneficial for analog circuits: significant noise and distortion problems appear, and many popular analog circuit topologies become unusable. This is a major problem for SoCs. The ADC topologies that are in use today do not scale well to low voltages.Time-based ADCs use a completely new approach in an attempt to solve the problem of voltage scaling. Analog information is first transferred to the time domain, where it is processed by purely digital circuits. Since this approach replaces most of the analog circuitry with digital logic, it can be used at much lower voltages and can benefit from transistor scaling just like other digital circuits.Several time-based ADC architectures have already been published in the past, however the performance of these designs is not sufficient to replace traditional architectures: the sampling rate is too low (usually below 100 MHz), the resolution is poor especially at higher sampling rates, and the power consumption is significantly higher than traditional designs that achieve similar speed and resolution.As part of this PhD we have developed a time-based ADC architecture that can compete with traditional ADC designs, i.e. an architecture that combines high speed with sufficiently high resolution while consuming minimal power. A prototype chip in 28nm CMOS implementing this new architecture achieved a worst-case SNDR of 45.2 dB at a sample rate of 5 GS/s, while consuming just 22.7 mW, resulting in a figure of merit of 30.5 fJ/cs. This is at least three times better than the best traditional ADC designs with similar speed and resolution published at the time. The design is also eight times smaller than comparable traditional ADCs.We realized that the frequency counter which was developed as part of this ADC would also be useful as a stand-alone frequency divider. This idea was further explored as a separate chip. Frequency dividers are often severely affected by PVT variations, so we combined the frequency divider with PVT-compensation and automatic tuning techniques to obtain an extremely wideband, PVT-tolerant frequency divider. A prototype chip in 28nm CMOS achieved a frequency range of 0.1 GHz to 67 GHz, corresponding to a locking range of 199.4%, which is very close to the theoretical maximum of 200%. To the best of our knowledge, the presented design is the first to combine such a wide locking range and high maximum frequency with automatic tuning and PVT compensation.

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