HW-algorithm co-design for approximate inference of probabilistic machine learning

In recent years, deep learning has gained tremendous attention for many challenging applications across the domains of computer vision, natural language processing, etc., and numerous computer platforms have been developed for these workloads. However, in applications with strict safety requirements or reliability requirements, for instance, self-driving vehicles, healthcare, and finance sector, it’s become crucial to perform reasoning and make the decision with uncertainty. For which, the “black-box” deep learning methods are not suitable. Probabilistic Machine Learning (ML) is able to quantify uncertainty and integrate expert knowledge. Researchers have also developed various kinds of exact and approximate inference algorithms for probabilistic ML. In this thesis, we will focus on the general solutions, sampling-based approximate inference, which is extremely compute-intensive. To meet the real-time and power constraints, a specific hardware accelerator should thus be designed. The following topic will be studied: • Workload: applications and inference algorithms: Markov Chain Mento Carlo (MCMC), such as HMC, Gibbs sampling, etc. • Computer architecture: Hardware architecture/co-processor design, extension towards sampling operation • Compiler: map the probabilistic programming to the chip