Testing of Circuits for Quantum Computers

Quantum computing offers a compute paradigm which is fundamentally different from the way in which today’s conventional computers operate. Its new capabilities benefit especially information processing and performing computationally hard tasks. Applications can be found in (1) cryptology and discrete mathematics for the factorization of large numbers into a product of primes (Shor’s Algorithm), (2) searching in large, unsorted databases (Grover’s Algorithm), (3) optimization problems (such as the well-known NP-hard ‘Traveling Salesman Problem’), and in (4) the simulation of other quantum systems, e.g., complex chemistry problems. Imec is one of the places where research is performed to implement quantum bits (‘qubits’), devices, circuits, and ultimately quantum computers. Imec’s quantum computing platforms focus on two alternative hardware platforms: ion traps/atoms and superconducting qubits. These quantum devices operate in a cryogenic setup at temperatures close to zero Kelvin. In this project, we intend to research the defects that can occur in silicon quantum devices and circuits as a basis to develop effective and efficient manufacturing tests. Can we define test procedures that can detect at ambient or at most mildly lowered or elevated temperatures devices that will not function well once brought into cryogenic conditions? Can we define test procedures, that can determine the volume of fully functional qubits available for usage by quantum algorithm? Can such test routines be implemented as either hardware- or software-based built-in self-test (BIST), thereby circumventing the need for external test equipment and hence enabling execution of these tests even when the device is in the cryogenic chamber?