High speed, radiation-tolerant optical and wireline communication circuits

Introduction Radiation-hard high-speed data links play an ever-growing role in modern High Energy Physics experiments. The state-of-the-art, marked by the lpGBT development for the LHC Phase-II upgrades, supports 10 Gb/s transmission and withstands radiation levels of 1 MGy and 10e+15 neq/cm². This is however already insufficient for some of the HL-LHC detectors where, for example, the pixel optoelectronics installed on the first strip layer requires the use of a massive number of lower-bandwidth copper cables. Another example is the case of the CMS HGCal detector, where the huge amount of data to be shipped off-detector with link bandwidths limited to 10 Gb/s will impose the installation of a large number of costly optical links. Experiments in future accelerators will demand even more bandwidth (especially when considering the trend towards trigger-less readout systems) and in some cases higher radiation hardness. Project description This Ph.D. project is a part of the Experimental-Physics Department research program for the development of detectors and detector systems for the future High Energy Physics experiments at CERN. The Ph.D. will center on the development of radiation-hard integrated circuits for transmission of data at very high data rates (>56 Gbps). In order to achieve those data rates, it will be necessary to use advanced modulation schemes – like, for example, Pulse Amplitude Modulation (PAM4) - that have not yet been demonstrated in the context of radiation-hardened circuits. To make future high data rate transmission systems practical, even when in presence of bandwidth-limited channels, the circuit will implement pre-emphasis techniques (intentional overdriving at the beginning of a transition). Throughout the Ph.D. research, a student will analyze the constraints imposed by the HEP detectors systems and the selected CMOS technology, study the existing state-of-the-art non-radiation-hard architectures for data communication systems and propose architectures suitable for CERN experiments. Subsequently, the practical implementation in the form of an Application Specific Integrated Circuit (ASIC) will be done which will require going through all phases of the design process (modeling, schematic entry, layout entry, simulations). Once the prototype ASIC is fabricated, functional evaluation and qualification of the chip will be done for use in radiation environments.