Memory technology for the terabit era: From 2D to 3D

© 2017 JSAP. Current stand-alone memory technologies for high density data storage are still based on electron-based principles that were established in the 1960s. While high bandwidth memories close to the CPU are still based on the 1T1C DRAM cell [1], also the nonvolatile space is still dominated by floating gate and charge trap concepts [2,3]. Meanwhile we have seen a major shift in the latter type, since Flash has made the jump to 3D monolithic integration, while, however, keeping with the same operating mechanisms. This transition has enabled a new roadmap by stacking ever more layers on the same chip. Although initially the technology was supposed to strongly lower the cost per bit [4], it turned out to be more expensive at first and several generations were needed to fully displace the planar floating gate concept, which essentially stopped scaling at the 15nm node [5]. In this paper this transition is discussed as well as its main limitations, and some suggestions are given for further scaling of 3D memories.

ISBN:9784863486058

Publication year:2017

BOF-keylabel:yes

IOF-keylabel:yes

Authors from:Government, Higher Education