Statistical Analysis and Modeling of Selectorless Non-filamentary Resistive RAM

Resistive switching memories are a class of emerging memories competing in several application domains, for example, Storage Class Memories and Internet of Things. Back-end-of-line compatible fabrication with possibility of stacking and scaling these devices make them attractive for high density applications. However, integrating these memory cells in an array leads to sneak path issues. A selector or access element can overcome this limitation but could involve additional processing or area constraints. A selectorless device with built-in non-linearity can alleviate these complexities. In this thesis, we study amorphous Vacancy Modulated Conductive Oxide (a-VMCO) self-rectifying selectorless devices in detail. The a-VMCO cell is a hybrid stack comprising a non-linear selector layer (amorphous Silicon) in series with a non-linear switching layer (anatase TiO2). The devices exhibit non-linear I-V characteristics with low reset and set switching currents. We demonstrate that the conduction and the switching is non-filamentary. The memory bit is stored in the spatial defect distribution in the TiO2 layer. Gradual and quasi-analog switching as well as area scaling are consequences of the multiple defect movements inside the switching layer. We use noise analysis technique to extract the current threshold above which significant transients occurs. Using the observations along with pulse monitoring experiments, it is inferred that the switching is mainly current-controlled. The nature of the defects and the underlying physics of the observed current-controlled transients is not known. So, we develop a physics-based and analytic kinetic defect distribution model with field- and current-driven defect movements and use it to understand and predict the device performance. Based on the simulations, we also propose an operation schematic to explain the transients. The reliability of the a-VMCO devices has been investigated in detail as well. The devices have low read-disturbs at operating read voltage. The variability in these devices is low, which can be attributed to the averaging effect of many defects in the switching layer. However, aggressive scaling in these devices would result in increased variability and localized effects. Long term cycle-to-cycle reliability is limited by the endurance failure. Post-cycling failure analysis using time-dependent dielectric breakdown and elevated temperature retention tests prove that defect loss intrinsically limits the endurance. Defects have to be dynamically generated to sustain cycling in a-VMCO devices. When the devices are allowed to relax under no applied bias, the defect distribution relaxes to the most stable state, i.e., uniform distribution, and the highest conductance is achieved. Discussing the reliability with respect to the model helps to identify and suggest directions for device improvement. The device has application opportunities in systems which require analog switching at low currents with low variability.