A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With-41.3-dB EVM at 1024 QAM in 28-nm CMOS

We present a subsampling polar transmitter (SSPTX) in 28-nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling phase-locked loop (PLL) and a harmonic rejection mixed (HRM) inverse-class-D (D -1 ) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar transmitter (TX), placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase errors but also to modulation amplitude. That feature enables AM-AM and PM-PM distortion to be detected and cancelled digitally in the background, while the transmitter operates normally. Moreover, the AM-PM cross distortion is filtered by the loop itself. The chip operates from a 0.9-V supply at 5.5 GHz with 2.5 MHz BW (1024 QAM) with average 1.1-dBm output power and total power consumption of 50 mW.

Publication year:2019

Keywords:Background calibration, digital-to-time converter (DTC), linearization, phase-locked loop (PLL), polar transmitter, subsampling, transmitter

CSS-citation score:2

Accessibility:Closed