A very low cost and highly parallel DfT method for analog and mixed-signal circuits

© 2017 IEEE. The quality level of the analog parts in mixed-signal ICs lags behind the below-part-per-million escape rates of the digital core. The reason is that analog blocks in these ICs have high test escape rates as a result of the typical testing based on performance specifications. Test point selection/insertion techniques have been proposed to solve this problem by offering increased observability. However, their effectiveness in practice is still limited due to the lack of a commonly accepted methodology to make probing of internal nodes in analog circuitry possible. This paper presents a low-cost and highly parallel DFT technique based on inserting testing diodes to internal circuit nodes, which enables those test point selection algorithms at low cost. An industrial case study demonstrates 90.4% fault coverage value with a very small overhead in area and test time.

ISBN:9781509054572

Publication year:2017

BOF-keylabel:yes

IOF-keylabel:yes

Authors from:Private, Higher Education

Accessibility:Open