FPGA design for large flow detection in high-speed networks

This project concentrates on the acceleration of large flow detection algorithms using configurable hardware. On the one hand, existing algorithms will be considered, which are effective and efficient for the detection of very large data flows, with a bandwidth that is, e.g., 100x larger than the allowed bandwidth. On the other hand, an algorithm-architecture co-design approach will be followed to develop novel algorithms and implementations for data flows that only exceed the allowed bandwidth to a limited extent. The goal is to integrate the configurable hardware in network devices and demonstrate efficient and effective protection against large flow network attacks.