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Project

Data placement in NVM hybrid scratchpad-cache hierarchies

Traditional memory technologies are facing significant limitations as the scaling process advances. The SRAM technology, typically used in different levels of on-chip cache hierarchies, is starting to show integration problems and a high static power consumption due to leakage currents. In recent years, several non-volatile memory technologies have been developed (PCM, ReRAM, STT-MRAM, SOT-MRAM, etc.) which solve some of the issues of traditional technologies but with important trade-offs, especially in latency and write energy.
In this research thesis, the candidate has explored different solutions to create an efficient memory system architecture. The problem has been approached by mixing different elements and creating heterogeneous memory organizations, both from a technology point of view (SRAM and STT-MRAM) and from a system management point of view (hardware controlled cache and software controlled scratchpad).
The research has been accompanied by a detailed feasibility study of the implemented changes, analyzing the energy and performance impact with standard benchmark sets. In the case of hybrid cache-scratchpad architectures, a custom data assignment policy has been developed as well, to decide which portions of data would best benefit from being manually managed. This work has required to setup an extensive profiling methodology, to extract memory access information from target applications, with the goal of detecting patterns and metrics to use for the placement decisions. Furthermore, it has been assumed that the designer does not necessarily have access to the original source code of applications, which entails operating on binaries for both the profiling and policies enforcement phases.
All the proposed modifications have been evaluated in the context of general-purpose embedded systems with consumption constraints, such as mobile devices, edge nodes or gateways. High level software device modelling and system simulation tools have been employed for the experimental part, with extensive modifications to fully represent the target architectures. In all the proposed configurations, it has been shown that it is possible to obtain substantial energy gains, with acceptable typical-case performance penalization.

Date:20 May 2019 →  20 May 2023
Keywords:hybrid hierarchy, sram, stt-mram, sot-mram, computer architecture, cache, scratchpad, nvram, memory mapping, optimization, memory technology, cpu
Disciplines:Memory management, Computer system architecture
Project type:PhD project