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Project
Fault-tolerant network-on-chip design
Network-on-chip (NoCs) possess high flexibility and scalability and thus represent an efficient approach for solving the communication problem in multi-core chips. However, it brings about reliability challenges. We focus on providing efficient strategies for mitigating both transient and hard errors in the NoC, for which we will develop fault-tolerant cache coherence protocols.
Date:1 Mar 2017 → 30 Jun 2020
Keywords:computer architecture, Network-on-chip, GPU
Disciplines:System software and middleware, Language processors, Computer architecture and networks not elsewhere classified, Processor architectures, Computer architecture and organisation, Computer hardware not elsewhere classified, Performance modelling, Computer system architecture, Performance evaluation, testing and simulation of reliability, Memory structures, Programming languages and technologies