RF ESD Exploration in Si/III-V Heterogeneous Integration for 5G/B5G Applications

When moving to the 5G telecommunication era, higher data rate and thus higher bandwidth are the main requirements to enable this evolution. For RF ESD protection design in traditional CMOS front-end module (FEM) circuits, the parasitic capacitance of the ESD protection devices should be as low as possible to meet the 5G bandwidth requirements. However, it is usually challenging to reduce the parasitic capacitance without sacrificing the ESD performance.

On the other hand, power efficiency of an RF power amplifier (PA) is critical to enhance the overall RF performance. In order to increase the power efficiency of the PA circuits, Gallium Nitride (GaN)-on-Si technology is consequently proposed to design the PA circuit in 5G communication systems. This technology can provide better high-power and high-frequency performances and a low-cost integration with the scaling CMOS process. The GaN PA eventually should be integrated with other CMOS FEM circuits by novel wafer-level heterogeneous integration techniques. When introducing the emerging GaN-on-Si technology and advanced integration techniques, ESD reliability evaluations should be adapted in order to provide appropriate ESD protection methods and evaluation tools in the specific technology.

In this work, first of all, a new tapered back-end-of-line (BEOL) layout structure was proposed and realized for the RF ESD co-optimization in advanced 28nm CMOS technology. Eventually, the improvement of the structure can be applied in a broadband ESD distributed protection network to enhance overall bandwidth at the 5G frequency bands.

Also, the ESD Human-Body Model (HBM) discharge model in GaN (MIS)- HEMTs is investigated, and it was found that the HBM conduction path is related to the Two-Dimensional Electron Gas (2DEG) channel conduction, and that the HBM failures show a mis-correlation with the Transmission-Line Pulse (TLP) test results. By the measured HBM transient I-V characteristics, the special HBM discharge mechanism of the 2DEG resistance modulation is revealed in both GaN MIS-HEMTs and HEMTs to explain the root cause of the HBM-TLP mis-correlation. Finally, the revised HBM correlation is derived with the consideration of the high 2DEG resistance in the saturation mode of the transistors.

In the last part of the thesis, a wafer-level Low-Impedance Contact Charged Device Model (LI-CCDM) tester is proposed for the potential ESD CDM issues in the advanced heterogeneous integrations. This LI-CCDM tester model is calibrated and verified by Vector Network Analyzer (VNA) measurements and SPICE simulations. Eventually, the parameters of the model can provide the instructions to optimize the LI-CCDM setup and to correlate to the JS-002 standard.

In conclusion, this thesis covered state-of-the-art issues of the 5G/B5G RF ESD strategies in the Si/III-V technology options and the development of the wafer-level CDM evaluation tools for the advanced heterogeneous integrations.