Advanced MIMO channel modeling and signal processing for highbitrate chip-to-chip interconnects prone to manufacturing variability (G013917N)

The advent of new electronic systems, operating at ever higher frequencies and bitrates, poses many challenges to the electrical engineer. Moreover, miniaturization is leading to an increased influence of manufacturing tolerances on the design. In this project, the focus is on a critical part of state-of-the-art electronic systems, namely the chip-to-chip links that interconnect driver and receiver Integrated Circuits (ICs –chips). The general design goal is to achieve an as high as possible data throughput (bitrate) with minimal energy consumption. To achieve this goal, novel multiple-input multiple-output (MIMO) signal processing schemes will be developed. MIMO has already boosted the bitrates of, e.g., mobile communications, but current signal processing for chip-to-chip interconnects is of the single-input single-output (SISO) type. Simultaneously, the effects of manufacturing variability on the links need to be investigated. At present, the Uncertainty Quantification (UQ) and the variability-aware analysis and design of realistic high-speed links is still missing. The MIMO signal processing schemes will be constructed in order to mitigate the adverse effects caused by this variability. The potential benefits of MIMO processing for chip-to-chip communications prone to manufacturing variability are largely unexplored. Nonetheless, the advocated approach is indispensable to satisfy the current and future needs of high-speed signaling in electronic devices and systems.