Integrated Time-based Signal Processing Circuits for Harsh Radiation Environments

This research focuses predominantly on the design and implementation of new architectures for integrated data converters based on time-based signal processing for applications requiring high levels of reliability in harsh radiation environments. The radiation-hardened integrated circuits (ICs) were designed with high radiation tolerance in mind, making them ideal for high energy physics (HEP) experiments, vital long-term space missions, and future nuclear-powered power plants. Mixed-signal interfaces, such as sensor readouts (resistive, capacitive, etc.) and clock interfaces, are integral components of a number of such mission-critical applications, and their reliable operation must be guaranteed. Long-term exposure to ionizing radiation causes total ionizing dose (TID) effects, which progressively alter the threshold voltage, charge carrier mobility, and leakage current of complementary metal-oxide-semiconductor (CMOS) transistors, thereby impacting the performance of analog and digital circuits. Single event effects (SEEs) are momentary disturbances generated by charge deposition in silicon (Si) when a charged particle impacts a sensitive node. In typical voltage or current-based signal processing, the analog-to-digital converters (ADCs) consist of multiple voltage amplifiers, integrators, and comparators, the performance of which is severely degraded by TID. Although TID effects can be mitigated by employing smaller technology nodes (thin gate-oxides), the impact of SEEs increases substantially. In scaled CMOS technologies, time-based circuits are relatively resistant to TID. Also, in harsh radiation environments, time-based techniques make it simpler to combat SEEs by employing radiation-hardened-by-design (RHBD) techniques (majority voters, functional redundancy, C-element, etc.). The synergy between scaled technologies and RHBD techniques benefits time-based signal processing over voltage domain signal processing.

As part of this Ph.D. research, three CMOS-based IC prototypes were implemented in 65-nm CMOS technology and then tested for performance validation and verification of proposed operating principles. Two distinct types of quadrature LC oscillators were implemented in the first experiment. X-ray irradiation up to 100 Mrad (= 1 MGy) was used to study the sensitivity of various prototype performance parameters with respect to TID. Next, a radiation-hardened time-based ΣΔ capacitance-to-digital converter (CDC) based on MASH 1-0 configuration was implemented. The prototypes were experimentally validated in the absence of radiation as well as in the presence of heavy-ion exposure (Xe-ion with LET of 65 MeV.cm2/mg). The CDCs were able to measure capacitance in the range 0-3.75 pF at 100 MHz with an ENOB of 12.9 bits. In the final project, a differential ΣΔ time-to-digital converter (TDC) with a Trange of 98 ns was implemented. It achieves 1st, 2nd, and 3rd orders of ΣΔ-modulation using a configurable time-based FIR filter in feedback.  In addition, the Ph.D. research was valorized by working with an industrial collaborator to develop a radiation-hardened frequency synthesizer. During the research valorization, several radiation-hardened components (a digitally-controlled oscillator, a multi-modulus divider, and output buffers) of an all-digital phase-locked loop (ADPLL) were implemented and characterized in different radiation conditions (TID, SEE and SEL).