Development of Reliable High-k Gate Dielectrics at Reduced Thermal Budget, for Integration on III-V Channels with Limited Thermal Stability and Sequential 3D Processing

Over the last years and decennia, the use of digital technology has increased up to the point where nearly every household has multiple laptops, tablets, mobile phones, ... . This technology has revolutionized multiple sectors (medicine, economics, communication, ...) and even most major security and defense systems now operate on this digital platform. However, as its importance gains, so does the request for faster, cheaper and more secure systems. This has not only put a lot of pressure on the ICT industry but also on the semiconductor industry, who is tasked with the development of new circuits and devices that meets these ever-increasing demands. Initially, this performance increase was achieved by simply making the elementary components (transistors) smaller so more could fit on the same area. However, we are now reaching sizes of only a 100th of a micrometer and with this are reaching the fundamental limits of silicon electronics. For this reason, people are looking into alternative way to continue the increase of the number of devices per unit area. One approach is to stack devices vertically, allowing higher densities to be achieved with similar devices. Another approach is the use of other materials that could allow for further scaling, higher performance and less power consuming electronics. One of the most promising materials are the so called "III-V" materials. While both approaches have very promising prospects, they all suffer from thermal instabilities to some extent. Unfortunately, the current device production process and knowledge that goes along with it all include high (800-1000°C) temperature steps. If these technologies are to be realized, in-depth knowledge on how to achieve sufficient performance and reliability under a restricted thermal processing conditions is needed. In this PhD project we propose to investigate one of the major roadblocks for these types of technologies, achieving sufficient high-k dielectric reliability at reduced thermal processing conditions. We aim to explore what happens to these materials when reducing the processing temperature, how this impacts their reliability and how we can use this to come to recommendations for the integration of these new concepts into the electronic devices of the future.