Design of high performance CMOS amplifiers for wireline communication

This doctoral research focuses on the integration of high performance line drivers for wireline communication in standard bulk CMOS technology. Among the many challenges are the realization of high linear output power for signals with a large PAPR together with a high efficiency. Generating high power in standard bulk CMOS technology is mostly limited by the low power supply voltage. In this research several circuit techniques (stacking, impedance transformation) are combined to generate high output power. These new designs are simulated, fabricated and measured.