Innovative solutions for advanced interconnects using ultralow-k dielectrics

Micro- and meso-porous materials have been widely studied for application in catalysis, gas separation, sensors, optics and so on. In semiconductor manufacturing, porous materials are also considered as inter-metal insulators with low dielectric constant (low-k) for ultra-large-scale integration (ULSI) interconnects. Various types of porous materials, including silica, pure polymer and metal organic framework, have been studied for interconnect applications. As critical dimensions scale down, advanced interconnects require low-k dielectrics in order to reduce power dissipation and resistance-capacitance (RC) signal delay. For porous organosilicate glass (p-OSG) materials, the currently most successful low-k candidate family, the material synthesis is well understood. The precursors, i.e. the silica matrix and the porogen, are co-deposited by plasma-enhanced chemical vapor deposition (PECVD) or sol-gel method. The porogen is then selectively removed, by annealing or (ultraviolet) UV-cure, to form a meso-porous structure. As such, continuous k value reduction is easily achieved by increasing the porogen/matrix ratio so as to generate higher open porosity. However, a larger porosity is generally accompanied by increased pore size. Highly porous structures lead to a low compatibility with conventional interconnect integration processing, for example, heterogeneous deposition, plasma processing and chemical mechanical planarization (CMP). Among them, low-k degradation by plasma etching and deposition of metal diffusion barrier is the most severe challenge. Plasma induced damage (PID) is mainly due to the penetration of etch radicals, photons and residues into the interconnected pores, resulting in a modified low-k structure and composition deep into the bulk. The loss of organic groups turns the pore sidewalls hydrophilic and subsequent moisture adsorption degrades the dielectric properties and reliability. Likewise, the penetration of metal-based species during physical-vapor or chemical-vapor deposition of the metal diffusion barrier causes issues of barrier continuity, leakage and effective dielectric constant. The ‘effective’ k-values for integrated inter-metal dielectrics are significantly higher than those of pristine materials. The increasing pore size also requires thicker barriers, which have such high resistivity that, for narrow lines, the use of Cu as metal does not allow anymore to reach the target line resistance. As a result, the integration of ultra-porous low-k dielectrics by state-of-the-art damascene technology meets huge challenges and k-value scaling is far below expectation.

In order to reduce the PID, many potential solutions have been put forward, including low damage plasma chemistry, post etch low-k repair, and post etch porogen burnout. In the meantime, several pore sealing approaches are proposed for better compatibility with deposition of metal diffusion barrier. However, all those solutions show either insufficient improvement or limited compatibility with the interconnects fabrication processes. This thesis focuses on three emerging integration strategies for advanced interconnects using ultralow-k dielectrics, namely, post porosity pore protection, pore protection by precursor condensation, and replacement low-k approach.

Since both plasma damage and barrier penetration issues originate from the porous structures, the densification of porous low-k is the most efficient way to improve the integration compatibility. Post porosity pore protection (P4) method is proposed as a solution enabling low damage integration of advanced porous low-k’s. This approach modifies the interconnect processing flow by introducing at an early stage an extrinsic sacrificial filler which suppresses the porosity of the low-k film. Pore protection process flow, including stuffing, etch and un-stuffing, has been extensively investigated in the present work. By optimization of the stuffing process conditions, various polymers can be filled successfully into p-OSG with different porosity and pore size. The penetration of polymers depends on the low-k structure, polymer properties and stuffing conditions. Temporary pore filling impedes the penetration of active radicals and the etch by-products during plasma processing. As a result, the PID is significantly decreased. Pore protection also enables defect-free metallization, which is of ultimate importance for successful integration of porous low-k’s. For this purpose, the sacrificial filler should be maintained during the whole metallization process, including the barrier deposition, Cu filling and chemical mechanical planarization (CMP). Low temperature and oxygen free de-stuffing approaches are required to avoid potential damage to the metallization structures.

Pore protection can also be achieved by an alternative strategy relying on low temperature pore filling with condensed precursor reactants. Plasma etch properties of porous organo-silicate materials at cryogenic temperature is studied. The mechanism of plasma damage is investigated by means of in-situ ellipsometry and post-etch material evaluation. Using conventional volatile reactants such as SF6, it is found that low plasma damage can be achieved below -120oC through two main channels: pore sidewall passivation by molecular SF6 and partial condensation of non-volatile etch by-products. The protection can be enhanced by means of gas phase precursors with low saturated vapor pressure. Using C4F8, complete pore filling is achieved at -110°C and negligible plasma-induced damage is demonstrated on both blanket and patterned low-k films. The characteristics of the precursor condensation process are described and discussed in detail, establishing an optimal process window. It is shown that the condensation temperature can be raised by using precursors with even lower vapor pressure. The in-situ densification through precursor condensation could enable damage-free plasma processing of mesoporous media. Compared with the P4 approach which requires additional stuffing and de-stuffing steps, the process flow using the cryogenic etch process offers a more simple and economic route for damage-free plasma processing of porous low-k materials.

Given the increasing difficulty of integrating advanced porous low-k, it makes sense to reconsider the subtractive approach, where the metal structure is defined first, followed by dielectric deposition. In spite of many research efforts on Cu direct etch and gap fill dielectric, there has been limited success in providing satisfactory morphological profile and electrical performance in technology-relevant dimensions. The present work investigates an alternative integration approach based on a “dielectric-last” scheme. The metal structure is first formed by patterning a sacrificial template material. After template removal, porous low-k dielectric is embedded into the spacing between the metal wires. The proposed method eliminates plasma-induced low-k damage, as well as barrier penetration issues. A Liquid Phase Self-Assembly low-k dielectric is used for the gap-filling purpose. By optimizing the spin coating conditions, void free gap-filling structures are achieved. The impact of low-k gap-filling process on the metal structures is investigated. The low-k porogen removal processes can induce formation of Cu2O and subsequent Cu migration, leading to detrimental electrical performance. Proper protection of the copper structures and tuning of the low-k curing process are thus adopted. Also, the integration scheme for dual damascene structure is explored. Formation of upper metal layers requires surface planarization on various gap-filling structures, which can be performed by chemical mechanical polishing. The surfactants present in the CMP slurry penetrate into the porous low-k, leading to dielectric degradation. A post cleaning step is therefore needed to remove the slurry residues and restore the k value to pristine level. Using a Meander-Fork integrated vehicle, the inter-metal dielectric properties are evaluated by RC and leakage current measurements. High electrical yield is obtained with integrated porous low-k showing promising effective k-values and breakdown voltages, confirming the promise of this specific integration approach.