Development of Reliable Gate Stacks for Stacked MOS Devices in a 3D Sequential Integration

In order to continue increasing the circuit functionality per area, a novel concept has been envisioned which consists of stacking transistors on top of each other sequentially in the same front-end process flow (“3D Sequential Integration”). This approach would enhance device density per chip area, without requiring further reduction of the device dimensions. Additional potential advantages include a simplified co-integration of heterogeneous devices technologies (e.g., Si and Ge/III-V channel FETs; logic and optical devices) and a reduction of the length of interconnection lines, with the associated beneficial reduction of signal propagation delays. The PhD research will focus on overcoming the gate stack challenges associated with the thermal budget constraints of a 3D Sequential Integration. These challenges are two-fold: on one hand, a sufficiently reliable high-k dielectric stack needs to be developed for the top layer without resorting to high temperature steps for defect curing. On the other hand, due to the limitations on the process temperature, doping activation and contact formation in the top transistor might need to be achieved with longer thermal steps, which might in turn affect the reliability of the bottom transistor (e.g., inducing undesirable diffusion of dopant atoms and other species present in the gate stack). As a consequence, the fabrication of the bottom devices might also need to be revised. The daily work will involve electrical and physical characterization of fabricated test structures (MOS capacitors and transistors); interpretation of the experimental trends based on modeling and simulations; definition of experiments and feedback to device integration engineers, in iterative learning cycles.