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Project

Ultra-low Leakage Power SRAM for Biomedical and IoT Applications

The Internet of Things (IoT) has brought about a huge growth in connected smart devices. These devices are mostly battery operated, but have low operating speed requirements, which enables low energy operation. When looking at state of the art microcontroller implementations for these devices, the leakage energy budget of the memory is prominent. This work highlights the significance of leakage optimisation in memories as a key enabler of energy- efficient microcontroller design without modifying the basic 6T cell topology, resulting in an area efficient design.

In a deep sub-micron technology, transistor variation introduces stability problems, which limits aggressive retention supply voltage scaling to reduce leakage. As a solution, this work uses the state of the art memory topology with local blocks to divide the stability problem into the local block level. Then, body biasing and voltage scaling are used on individual blocks to achieve retention closer to the point of first failure for the entire memory. However, individual tuning of local blocks requires monitoring of these blocks. Thus, the thesis shows two methods of monitoring: analog monitoring to estimate the static noise margin and digital monitoring using forward error correction codes. The latter enables operation beyond the point of first failure. Furthermore, the local block division saves leakage power by extending the time spent in retention. Only a single local block is switched to access mode.

These monitoring and compensation techniques are validated in two prototype chips. The first prototype shows analog monitors and body bias compensation. Selective body biasing can increase the static noise margin with 50mV. As a result, the cell array leakage power is reduced with more than 50%. The second prototype shows a forward error correction code monitoring and voltage scaling compensation. Here, the cell supply of the uncompensated cells can be reduced from 300mV to 170mV, resulting in a 70% decrease of leakage power. When using the second prototype in a recording application, it shows the lowest total power consumption compared to other state of the art memory macros.

Date:1 Oct 2017 →  1 Feb 2024
Keywords:SRAM
Disciplines:Nanotechnology, Design theories and methods
Project type:PhD project