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Researcher
Jorge Luis Lagos Benites
- Keywords:Electronics and electrical engineering
Affiliations
- Faculty of Engineering (Faculty)
Member
From19 Aug 2015 → 2 May 2019 - Electronics and Informatics (Department)
Member
From12 May 2014 → 11 May 2018
Publications
1 - 7 of 7
- A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS(2022)
Authors: Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Jan Craninckx
Pages: 2068-2077 - A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC(2021)Series: ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
Authors: Ewout Martens, Jorge Luis Lagos Benites, Benjamin Hershberg, Jan Craninckx
Pages: 207-210Number of pages: 4 - A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers(2019)
Authors: Jorge Luis Lagos Benites, Benjamin Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
Pages: 646-658 - High-performance, power-efficient ADCS based on ring amplification(2019)
Authors: Jorge Luis Lagos Benites, Jan Craninckx, Piet Wambacq
- High-performance, Power-ef?cient ADCs Based on Ring Ampli?cation(2019)
Authors: Jorge Luis Lagos Benites
- A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS(2018)
Authors: Jorge Luis Lagos Benites, Benjamin Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
Pages: 403-416 - A Single-Channel, 600Msps, 12bit, Ringamp-Based Pipelined ADC in 28nm CMOS(2017)
Authors: Jorge Luis Lagos Benites, Benjamin Hershberg, Ewout Martens, Jan Craninckx
Pages: C96-C97Number of pages: 2