Researcher
Diederik Verkest
- Keywords:Electronics and electrical engineering
- Disciplines:Engineering and technology
Affiliations
- Multidimensional signal processing and communication (Research group)
Member
From1 Jan 2005 → 31 Dec 2006 - Electronics and Informatics (Department)
Member
From1 Oct 2001 → 30 Sep 2014
Publications
1 - 10 of 14
- Device-, Circuit-Block-level evaluation of CFET in a 4 track library(2019)Series: Digest of Technical Papers - Symposium on VLSI Technology
Authors: P. Schuddinck, O. Zografos, P. Weckx, Pierre Matagne, S. Sarkar, Yasser Sherazi, R Baert, D. Jang, D Yakimets, Akhil Gupta, et al.
Pages: T204-T205 - Power-performance trade-offs for Lateral NanoSheets on ultra-scaled standard cells(2018)Series: Digest of Technical Papers - Symposium on VLSI Technology
Authors: M. Garcia Bardon, Yasser Sherazi, D. Jang, D Yakimets, P. Schuddinck, R Baert, Hans Mertens, L. Mattii, Bertrand Parvais, Anda Mocuta, et al.
Pages: 143-144Number of pages: 2 - Scaling CMOS beyond Si FinFET(2018)Series: European Solid-State Device Research Conference
Authors: Bertrand Parvais, G. Hellings, M. Simicic, P. Weckx, J. Mitard, D. Jang, V. Deshpande, B. Van Liempc, A. Veloso, A. Vandooren, et al.
Pages: 158-161Number of pages: 4 - Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology(2018)Series: Technical Digest - International Electron Devices Meeting, IEDM
Authors: D Yakimets, M. Garcia Bardon, D. Jang, P. Schuddinck, Yasser Sherazi, P. Weckx, Kenichi Miyaguchi, Bertrand Parvais, Praveen Raghavan, A. Spessot, et al.
Pages: 20.4.1-20.4.4 - Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs(2016)
Authors: Bao Trong Huynh, Julien Ryckaert, Sushil Sakhare, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Piet Wambacq
Number of pages: 12 - A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs(2016)
Authors: Bao Trong Huynh, Sushil Sakhare, Julien Ryckaert, Dimitri Yakimets, Aaron Thean, Abdelkarim Mercha, Diederik Verkest, Piet Wambacq
Pages: 643-651 - A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS(2016)
Authors: Bertrand Parvais, Piet Wambacq, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Ken Sawada, Kazuki Nomoto, Tetsuya Oishi, Hiroaki Ammo
Pages: 157-160 - Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM(2015)
Authors: Bao Trong Huynh, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Piet Wambacq
Pages: 1-4Number of pages: 4 - Vertical device architecture for 5nm and beyond: device & circuit implications(2015)
Authors: AV-Y Thean, Dimitri Yakimets, Bao Trong Huynh, P. Schuddinck, Sushil Sakhare, M Garcia Bardon, A. Sibaja-Hernandez, I Ciofi, G. Eneman, A Veloso, et al.
Pages: 26-27 - Modeling FinFET metal gate stack resistance for 14nm node and beyond(2015)
Authors: Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Praveen Raghavan, A. Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean
Pages: 1-4