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Researcher
Hans Reyserhove
- Disciplines:Nanotechnology, Sensors, biosensors and smart sensors, Other electrical and electronic engineering, Design theories and methods
Affiliations
- Electronic Circuits and Systems (ECS) (Division)
Member
From1 Aug 2020 → 30 Sep 2018 - ESAT - MICAS, Microelectronics and Sensors (Division)
Member
From15 Mar 2011 → 30 Sep 2018
Projects
1 - 1 of 1
- Efficient design of ultra-low power nearthreshold digital processors.From2 Jul 2012 → 12 Sep 2018Funding: IWT personal funding - strategic basic research grants
Publications
1 - 7 of 7
- Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40nm CMOS(2018)
Authors: Hans Reyserhove, Wim Dehaene
Pages: 2101 - 2113 - Design Margin Elimination in a Near-Threshold Timing Error Masking-Aware 32-bit ARM Cortex M0 in 40nm CMOS(2017)
Authors: Hans Reyserhove, Wim Dehaene
Pages: 155 - 158 - A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs(2017)
Authors: Hans Reyserhove, Wim Dehaene
Pages: 1904 - 1914 - A 16.07pJ/cycle 31MHz Fully Differential Transmission Gate Logic ARM Cortex M0 core in 40nm CMOS(2016)
Authors: Hans Reyserhove, Wim Dehaene
Pages: 257 - 260 - Ultra-Low Voltage Datapath Blocks in 28nm UTBB FD-SOI(2014)
Authors: Hans Reyserhove, Nele Reynders, Wim Dehaene
Pages: 49 - 52 - Design Margin Elimination Through Robust Timing Error Detection at Ultra-Low Voltage
Authors: Hans Reyserhove, Wim Dehaene
Pages: 1 - 3 - Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors
Authors: Hans Reyserhove, Wim Dehaene
Number of pages: 276